Modern-day technological advancements have led to the increasing amounts of data being transmitted and received. Security, being one of the major concerns, several data encryption algorithms have been employed to protect the data from fraudulent usage. Out of the several algorithms, AES has been widely accepted for providing higher degree of confidentiality and simplicity in implementation. Several modifications have been suggested by researchers in enhancing the security of this algorithm. This work presents a novel technique for dynamic S box generation in AES cryptography. The module used for key expansion of the AES implementation is modified to reduce the power consumption and the area occupied by the structure. The proposed method of implementation using NAND gates can be used in FPGAs for reduced power consumption when compared to the normal implementations. In this work, a novel method for implementation of Substitution BOX using NAND gates is presented and the effectiveness of hardware implementation and its power requirements are presented. This implementation of Advanced encryption standard is carried out with Cadence Virtuoso. The implementation of AES algorithm is being carried out in secure file transfer protocols like FTPS, HTTPS.