Article

Jayasanthi, M and Kowsalyadevi, A K (2019) Low Power Implementation of Linear Feedback Shift Registers. International Journal of Recent Technology and Engineering (IJRTE), 8 (2). pp. 2375-2379. ISSN 22773878

Subash Kumar, C S (2019) Implementation of Low Power Null Conventional Logic Function for Configuration Logic Block. Wireless Personal Communications, 107 (4). pp. 2231-2245. ISSN 0929-6212

Book Section

Gowsika, D and Ashwin Kumar, S and Chandra Prakash, S and Reba, P (2023) Low power designs for enhanced CMOS performance. In: Low Power Designs in Nanodevices and Circuits for Emerging Applications. CRC Press, Boca Raton, pp. 213-253. ISBN 9781003459231

Conference or Workshop Item

Deepa, M and Varssha, B and Srivarsa, T and Hariprasath, K (2023) Performance Analysis of FPGA Implementation of 4 x 4 Vedic Multiplier using different adder architectures. In: 2023 Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT), Trichirappalli, India.