D

Deepa, M and Devarapalli Anirudh, Reddy and Hariprasath, K and Rohit, N and Yedusheker, S (2024) Design of Efficient Approximate Unsigned Multiplier using VariousApproximate Compressor Configurations. In: 2024 International Conference on Smart Systems for Electrical, Electronics, Communication and Computer Engineering (ICSSEECC), Coimbatore, India.

Deepa, M and Varssha, B and Srivarsa, T and Hariprasath, K (2023) Performance Analysis of FPGA Implementation of 4 x 4 Vedic Multiplier using different adder architectures. In: 2023 Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT), Trichirappalli, India.

G

Gowsika, D and Ashwin Kumar, S and Chandra Prakash, S and Reba, P (2023) Low power designs for enhanced CMOS performance. In: Low Power Designs in Nanodevices and Circuits for Emerging Applications. CRC Press, Boca Raton, pp. 213-253. ISBN 9781003459231

J

Jayasanthi, M and Kowsalyadevi, A K (2019) Low Power Implementation of Linear Feedback Shift Registers. International Journal of Recent Technology and Engineering (IJRTE), 8 (2). pp. 2375-2379. ISSN 22773878

P

Paldurai, K and Deepesh, M and Prasanna Kumar, K and Kishore, C and Deepak, K (2024) Optimizing Multiplier Performance with Advanced PTL-Based AND Gate and Efficient Full Adder Design. In: 2024 International Conference on Smart Systems for Electrical, Electronics, Communication and Computer Engineering (ICSSEECC), Coimbatore, India.

Paldurai, K and Kamali, S and Muthukumaran, M (2024) Design of Adaptive Ramp Generator. In: 2024 International Conference on Smart Systems for Electrical, Electronics, Communication and Computer Engineering (ICSSEECC), Coimbatore, India.

Paldurai, K and Srivarsa, T and Ashwin Kumar, S and Bharath Ram, K and Chandra Prakash, S (2024) UVM Verification of RISC-V Instruction set. In: 2024 International Conference on Smart Systems for Electrical, Electronics, Communication and Computer Engineering (ICSSEECC), Coimbatore, India.

S

Subash Kumar, C S (2019) Implementation of Low Power Null Conventional Logic Function for Configuration Logic Block. Wireless Personal Communications, 107 (4). pp. 2231-2245. ISSN 0929-6212

V

Vijayakumar, P and Bhuvaneswari, K and Bhuvaneshwari, S (2024) Adiabatic Logic: A Paradigm Shift in Power-Efficient VLSI Design for FIR Filters. In: 2024 International Conference on Smart Systems for Electrical, Electronics, Communication and Computer Engineering (ICSSEECC), Coimbatore, India.