Low power designs for enhanced CMOS performance

Gowsika, D and Ashwin Kumar, S and Chandra Prakash, S and Reba, P (2023) Low power designs for enhanced CMOS performance. In: Low Power Designs in Nanodevices and Circuits for Emerging Applications. CRC Press, Boca Raton, pp. 213-253. ISBN 9781003459231

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Abstract

This chapter focuses on different low-power CMOS circuit techniques that can be generally applied to almost any kind of digital circuits. First, it gives the basic understanding of the sources of power dissipation. Second, the fundamentals of different static and dynamic logic techniques are discussed. As dynamic power dissipation has a quadratic relation with the supply voltage, it proves to be the dominant component and is the major concern presented here. The impact of voltage scaling and its effects are discussed in detail. Various threshold voltage control techniques such as MTCMOS, VTCMOS, DTCMOS and Dual-V th CMOS in order to mitigate the problems caused by reducing the voltage, subthreshold leakage current, and many others give a fundamental understanding. Finally, a comparative analysis of different domino logics is presented.

Item Type: Book Section
Subjects: D Electrical and Electronics Engineering > Power Transformers
E Electronics and Communication Engineering > VLSI (Low Power)
E Electronics and Communication Engineering > Integrated Circuits
Divisions: Electronics and Communication Engineering
Depositing User: Users 5 not found.
Date Deposited: 19 Aug 2024 09:59
Last Modified: 19 Aug 2024 10:00
URI: https://ir.psgitech.ac.in/id/eprint/949

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