This paper describes an area-efficient AES design method that takes into account the implementation features of application-specific integrated circuits (ASIC) and field-programmable gate arrays (FPGA). The majority of the AES hardware area is occupied by Sub bytes and MixColumns, hence this paper concentrates on optimizing and assessing their design approach. This short examines the trade-off connection between area and clock cycles based on data channel changes and proposes an area-efficient AES intellectual property (IP) design. This paper provides a 128-bit AES design based on text data cryptography. Verilog HDL program is used for implement the design, in addition to that Modelsim is used here to simulate the results. With the help of Synthesis Process of the Xilinx is used for measuring the performance. This work provides a 128-bit AES design based on text data cryptography. The designed architecture has been implemented in FPGA-XC3S 200 TQ-144 using Verilog HDL