Paldurai, K and Srivarsa, T and Ashwin Kumar, S and Bharath Ram, K and Chandra Prakash, S (2024) UVM Verification of RISC-V Instruction set. In: 2024 International Conference on Smart Systems for Electrical, Electronics, Communication and Computer Engineering (ICSSEECC), Coimbatore, India.
Full text not available from this repository.Abstract
This paper introduces a comprehensive verification methodology tailored specifically for RISC-V processors, leveraging the power of the Universal Verification Methodology (UVM). With its open standard architecture, RISC-V stands out for its simplicity and efficiency, making it a preferred choice across diverse application domains. The utilization of UVM, a suite of standard tools and APIs, enhances the robustness of the verification process for RISC-V designs and Systems on Chip (SoCs). The proposed methodology encompasses various critical aspects, including the design of testbenches, implementation of agents, generation of stimuli, and adoption of coverage-driven verification techniques. Through meticulous execution of tests, careful monitoring of instruction flows, and comprehensive summaries of simulation results, the study showcases the effectiveness and reliability of the proposed methodology in thoroughly scrutinizing RISC-V processors. This approach not only ensures the correctness and reliability of RISC-V designs but also sets a standard for future verification strategies, potentially leading to advancements in the verification process for emerging architectures.
Item Type: | Conference or Workshop Item (Paper) |
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Uncontrolled Keywords: | Design under tests; Instruction set architecture; Reduced instruction set architecture - version five; Reduced instruction sets; Universal verification; Universal verification method; Verification method; Verification methodology; Verification process |
Subjects: | E Electronics and Communication Engineering > Circuit Design E Electronics and Communication Engineering > Integrated Circuits |
Divisions: | Electronics and Communication Engineering |
Depositing User: | Dr Krishnamurthy V |
Date Deposited: | 28 Sep 2024 08:18 |
Last Modified: | 28 Sep 2024 08:18 |
URI: | https://ir.psgitech.ac.in/id/eprint/1236 |