Multipliers are combinational circuits used to multiply binary digits. A multiplier circuit is commonly used in a variety of applications, including digital signal processing such as convolution, and filtering, audio and video processing, communication systems, etc. The multiplication process is carried out initially by generating the partial products (PP) and then summing them up to get the result. Due to the complexity of the multiplication operation and the number of operations needed to complete it, multiplier circuits typically use more power than other types of circuits. In a multiplier circuit, two numbers are multiplied by performing several additions and bit-shifting operations. Particularly when working with larger operands or operating at high frequencies, these processes demand a sizeable amount of power. There are several ways to improve the efficiency of the multiplier such as reducing the number of logic levels, using hardware acceleration like FPGA boards, etc. This study proposes an effective multiplier architecture that uses modified hybrid full adders (FA) and partial product generation using pass transistor logic (PTL) for AND gate. This architecture was to the conclusion after comparison of components such as AND gate, and Full Adders (FA) simulated under various designs using CMOS and TG logics. The suggested multiplier has good performance and low power consumption, making it a perfect option for digital signal processing applications.