The reduced instruction set computing (RISC) architecture is a free and open Instruction Set Architecture (ISA), which enables a new era of processor innovation through open standard collaboration. It directly challenges several well-established processor families such as intel x-86, Motorola 68k processor. To thrive an RISC-V ecosystem, the core suppliers need an independent verification solution to ensure that their designs are compliant with the ISA specification. Verification of RISC-V designs become challenging due to their optional features, implementation flexibility, and provisions for customer extensions. Hence, a thorough verification is essential to compete successfully against the established processor families. Automation is the key for reducing the time taken for the processor verification. This paper provides a way to develop an automated tool ATGP_RISC-V, which uses the same arguments to run all instruction generators. This helps in verifying the processor in an efficient way by reducing the time taken to manually compare the test results.