The Existing and emerging information and communication technology (ICT) applications, such as smart cities, internet of things (IOT), autonomous vehicles, among other things, need more effective electronic and control systems and smaller sizes. This is a challenging problem for electronic designers to design such a system with low power consumption short development times and miniature in size for a world market. The development of chip-based systems (SOC) is an attractive and viable solution because SOC technologies allow customized designs for nanometric and low power consumption architectures and technologies. A SOC is developed by combining several previously designed and tested tiny modules. These modules are called as intellectual properties or IP cores for semiconductors. This work describes single, double and multiple precision multipliers for better timing and area performance. To achieve higher accuracy normalization is applied to the multiplier algorithm. The architecture design is implemented by Verilog HDL. Simulation is done by Modelsim 6 and synthesis done by Xilinx tool.