The Digital signal processing (DSP) algorithms often involve numerous mathematical operations performed rapidly and repeatedly on a dataset. Many DSP applications face power consumption constraints, necessitating a MAC (Multiplier-Accumulator) unit that offers high speed, throughput, and low power consumption. In this research, we employed a Booth multiplier to reduce power consumption in the MAC (Multiply-Accumulate) unit, given its lower power consumption compared to alternative multipliers such as the Array multiplier and Wallace tree multiplier. As for the adder module, we opted for a Ripple Carry Adder, evaluating its power consumption in comparison to Carry Lookahead and Carry Save adders. The MAC unit, integrating the Booth multiplier and Ripple Carry Adder, was implemented using 45nm CMOS technology within the Cadence Virtuoso Tool.The results suggest that the suggested MAC unit demonstrates a decrease in power usage. Specifically, the power consumption of the MAC unit utilizing the proposed design is 0.65 mW.