BIST circuits have been increasingly used to test the data converters and evaluate the errors in the same. A BIST scheme that completes the computation of the differential and integral non-linearity errors of an ADC in a single ramp cycle, unlike the histogram-based methods, which re- quire multiple ramp cycles, has been proposed. A counter calculates the number of ticks in each output code before the next code transition is detected by the designed code change detector module. The difference between the ideal code width and the obtained width is evaluated for each code to compute the maximum DNL. The cumulative DNL is calculated to determine the maximum INL. This time- tick-based proposed scheme was designed and simulated to enumerate the results. The computational accuracy is found to increase when the clock frequency and the ideal code width are increased. The proposed technique eliminates the use of external memory present in previous work based on time-tick, takes less testing time and is highly scalable.