Elliptic curve cryptography (ECC) over binary finite fields relies heavily on polynomial multiplication, making the efficiency of the underlying multiplier architecture a critical factor in cryptographic hardware design [23]. Among various approaches, Karatsuba multiplication is widely adopted due to its reduced arithmetic complexity; however, aggressive parallelism and improper resource reuse often lead to excessive power consumption and thermal infeasibility on FPGA platforms [11, 26]. This paper presents a comprehensive architectural exploration of seven 256-bit Karatsuba-based binary polynomial multiplier architectures over Galois Field (GF) (2256), each employing a different resource-reuse strategy ranging from fully parallel to fully sequential implementations. All architectures are implemented on a Xilinx Artix-7 FPGA using identical synthesis and power estimation settings to ensure a fair comparison in terms of area, latency, power consumption, and junction temperature. The study reveals that fully parallel Karatsuba architectures, although fast, are thermally impractical due to excessive switching activity, while fully sequential designs suffer from high latency. Based on these insights, a balanced resource-reuse architecture is identified, which selectively reuses multiplier blocks from 16-bit to 128-bit levels while retaining parallelism at lower levels. Compared to the fully sequential Karatsuba architecture, the proposed balanced design reduces computation latency by more than 26 × (121 cycles vs. 3280 cycles) while maintaining thermally safe operation (73.0 °C) and consuming only 18% higher power (25.66 W vs. 21.77 W). This balanced trade-off makes the proposed architecture particularly suitable for FPGA-based ECC accelerators requiring both performance and energy efficiency.