The two main problems with testing integrated chips of the current generation are testing power and testing expense. Test data amount and transmission time are connected to testing costs. In addition to increasing memory needs, larger data volumes also result in longer testing times. In scan-based test applications, several effective test data compression methods are suggested to reduce test time and test data volume at the same time. To improve the compression ratio, the test data is compressed using a combination of the compatible block coding and Huffman coding technique is first proposed method. Second proposed method is Hamming coding, Bitmask dictionary, and the 2nPattern Run Length coding algorithm were combined to create hamming coding and BDPRLC, which compresses test data in order to increase the compression ratio. A decompression algorithm was implemented using VHDL program. MATLAB code was used to implement compression method, and the compression ratio for different circuits was assessed using test vectors of benchmark circuits, ISCAS 89.