Multiplication plays a major role in the signal and image processing applications. The reduction of partial products was done using full adders and half adders, which increases the computation complexity, area and power. This paper presents a highly efficient four to two approximate compressor with less error probability and applied in multipliers of various configurations. The proposed approximate compressor is implemented in the design of Wallace tree multiplier. Experimental results shows increase in performance, less area and less power compared with adder based partial product reduction, exact compressor and state of art approximate compressors.