The demand for high-performance hardware accelerators is growing, which are widely used nowadays for implementation of Deep Learning methods like that of Convolutional Neural Networks (ConvNet / CNN) on reconfigurable devices. The Multiply-Accumulate (MAC) units are the warhorses behind the remarkable speed and efficiency of convolution operations. Double MAC approach combines two units of MAC operations into a single Digital Signal Processing module of a reconfigurable Field Programmable Gate Arrays (FPGA), thereby increasing the throughput of Convolutional Neural Network accelerators. By dynamically adjusting the precision of MAC operations to 4-bit, 8-bit, and 16- bit fixed and floating-point representations, MAC units can be optimized for efficient resource utilization and power consumption. In this paper, a Double multiply-accumulate unit, dynamically changing precision with 8-bit and 16-bit, is proposed. By leveraging the inherent parallelism and pipelining capabilities of Field Programmable Gate Arrays (FPGA), Double multiply-accumulate approach optimizes the utilization of hardware resources while minimizing the power consumption. The flexible precision scaling in the proposed work proves advantageous in convolution layers, where greater precision is required for final classification and smaller precision in initial stage. Simulation, Synthesis and FPGA Implementation of the proposed Double MAC unit with dynamic precision scaling have been done and it is found successful. The proposed Double MAC approach has showed twofold improvement in throughput and 15% improvement in power consumption. These techniques are highly useful for fast data processing in wireless communication.