Convolution is a fundamental operation in digital signal processing and machine learning, and its efficiency strongly depends on the underlying multiplier architecture. This works conducts a detailed evaluation of Braun, Booth and Wallace tree multipliers on FPGA platforms, focusing on their role within convolution operations. The 32×32-bit designs were developed in Verilog HDL and synthesized using Xilinx Vivado, with performance measured in terms of delay, logic resources, and power efficiency. The Booth design exhibited the lowest power consumption (61.418 W) and smallest area (1026 LUTs), but introduced a longer delay (33.969 ns). The Braun structure provided a moderate balance with 21.428 ns delay, 81.587 W power, and 1073 LUTs. In contrast, the Wallace tree was the fastest (21.488 ns), though it consumed the most resources (115.416 W, 1479 LUTs). Within a 3-tap FIR convolution module, the dedicated DSP multiplier proved the most efficient (37.828 W, 15.594 ns, 68 LUTs). Substituting it with a Booth multiplier raised both power (62.979 W) and delay (18.903 ns), while leaving the area nearly unchanged (69 LUTs). Overall, DSP slices remain the most efficient choice for FPGA convolution, though Booth multipliers offer a compact alternative, Braun designs provide modularity, and Wallace trees trade power and area for speed.