This paper presents an open-source, modular five-stage pipelined RISC process or developed using Verilog for teaching and proto typing applications in computer architecture. Unlike many academic designs, this framework emphasizes modularity, extensibility, and accessibility, making it ideal for education and early-stage research. The design includes a custom instruction set, clear architectural documentation, and cycle-accurates imulations, enabling students and researchers to thoroughly explore process or behavior, pipelining concepts, and hazard scenarios. Extensive simulation-based validation provides detailed insight in to instruction execution flow, control signals, and pipeline interactions. By bridging theory with practical, hands-on exploration through openly available source code and simulation resources, this work offers a reproducible and adaptable platform for students, educators, and researchers studying RISC architectures, pipelining, and hardware verification.